1. Field of the Invention
The present invention relates to semiconductor devices and methods of testing a semiconductor device. More specifically, the present invention relates to a semiconductor device having a plurality of memory regions and a function of self-testing the contained memory regions as well as a method of testing a semiconductor device.
2. Description of the Background Art
As semiconductor devices have higher functions and memories with larger capacity in recent years, BISTs (built-in self tests) have increasingly been adapted to reduce test cost.
FIG. 23 is a block diagram showing a configuration example of a conventional semiconductor device 260 including the BIST function.
Referring to FIG. 23, semiconductor device 260 includes an input buffer 34 receiving a control signal for self testing (hereinafter, referred to as a self test control signal) BISTIN, a BIST circuit 262 initiating a self test according to an output of input buffer 34, input buffers 20 to 26 receiving control signals BA, /RAS, /CAS, /WE, an input buffer 28 receiving an address signal AD, an input buffer 30 receiving a data input signal DI, and an output buffer 32 outputting a data output signal DO.
Semiconductor device 260 further includes a memory array 2a, as a bank A, which has a plurality of word lines WL, a plurality of bit lines BL, and memory cells corresponding to the crossings thereof, a corresponding row address decoder 4a and column address 6a, a memory array 2b as a bank B, and a corresponding row address decoder 4b and column address 6b.
Semiconductor device 260 further includes a spare row 8a, a spare row address decoder 10a, a spare column 12a, and a spare column address decoder 14a to repair a defective memory cell existing in memory array 2a. Similarly, semiconductor device 260 further includes a spare row 8b, a spare row address decoder 10b, a spare column 12b, and a spare column address decoder 14b to repair a defective memory cell existing in memory array 2b.
In the normal operation, semiconductor device 260 transmits data to contained banks A, B according to externally input control signals BA, /RAS, /CAS, /WE, address signal AD, and data input signal DI.
In the test operation, self test control signal BISTIN is activated. In response, input buffer 34 activates BIST circuit 262 and inactivates input buffers 20 to 30 and output buffer 32. BIST circuit 262 outputs an internal bank address signal BAI, an internal row address strobe signal /RASI, an internal column address strobe signal /CASI, an internal write control signal /WEI, and an internal address signal ADI. Banks A, B transmit data according to the control signals and the address signal output by BIST circuit 262. At this time, internal data signal IDI is generated by a prescribed algorithm in BIST circuit 262. Further, an internal data output signal IDO read from banks A, B is received in BIST circuit 262 to verify if it matches an expected value.
FIG. 24 is a block diagram showing a configuration of BIST circuit 262 shown in FIG. 23.
Referring to FIG. 24, BIST circuit 262 includes a control signal generator 264 activated by self test control signal BISTIN, receiving a clock signal for testing (hereinafter, referred to as a test clock signal) BISTCLK, and outputting internal control signals /RASI, /CASI, /WEI, an address generator 266 activated by self test control signal BISTIN, receiving test clock signal BISTCLK, and outputting internal address signal ADI and internal bank address signal BAI under the control of control signal generator 264, a data generator 268 activated by self test control signal BISTIN, receiving test clock signal BISTCLK, and generating, during self testing, write data to be written to a memory bank and expected value data of data read from the memory bank, and a data comparator 270 comparing an output of data generator 268 and internal data output signal IDO read from a memory bank. An output of data comparator 270 is externally output as a signal BISTOUT.
When the address of a cell to be repaired is stored in a register and the defective memory cell is repaired according to this information during self testing, a register capable of storing address information corresponding to the defective memory cell to be repaired is at least necessary.
Since a memory array is generally formed of rows and columns, replacement with spare rows and columns is carried out on the basis of a row and a column even for repairing defective memory cells.
For a series of defective cells on the same row or column caused, for example, by a word line or bit line defect, an optimum solution to replacement is inevitably found. It is easy to determine whether a semiconductor device having only such defects can be repaired.
For such a defect of a single memory cell that is called a bit defect, it is possible to repair the memory cell by replacement with either a spare row or a spare column. In order to carry out optimum replacement in a semiconductor device having such a bit defect, it is necessary to make a calculation based on the distribution of defective memory cells in the entire memory array and the number of redundant rows and columns capable of replacing defective ones. Finding an optimum row and column to be replaced is called repair solution finding.
When a register having only information on a row or column to be replaced is used, an optimum repair solution to a bit defect cannot be found, which results in a reduction in the repair rate.
FIG. 25 is a diagram for describing a configuration of a conventional memory tester for finding an optimum solution to a bit defect.
Referring to FIG. 25, test flows and test conditions according to test manners are programmed in an IC tester control CPU 851 of an IC tester 850. IC tester control CPU 851 applies a control signal to each circuit of IC tester 850 through a control signal transmission bus 852 if necessary and sets data for each circuit. A reference signal generation circuit 853 generates an operation reference signal for IC tester 850. The reference signal becomes the basis of a cycle in which test waveform conditions are changed (hereinafter, referred to as a test cycle). The reference signal is applied to a timing generator 855 and a program power supply 860.
Timing generator 855 controls the timing of a test waveform change, for example. A test pattern storing circuit 856 determines the pattern of a test waveform for each test cycle. A functional test pattern generator 857 which is formed of a high speed microcomputer generates address and data to be applied to devices under test DUT1 to DUTn, and controls clocking. A format circuit 858 produces a test waveform by synthesizing for each test cycle a timing signal applied from timing generator 855, a test pattern applied from test pattern storing circuit 856, and logical data applied from functional test pattern generator 857. Timing generator 855, test pattern storing circuit 856, and format circuit 858 constitute a waveform formation circuit 859.
Program power supply 860 is formed of a bias voltage supply unit supplying devices under test DUT1 to DUTn with power supply voltage, and a data level power supply determining the level of drivers and comparators in pin electronics 861. Pin electronics 861 is formed of drivers, comparators, and relays connecting them to devices under test DUT1 to DUTn. Pin electronics 861 determines, by using the contained comparators, whether the output waveforms of devices under test DUT1 to DUTn are normal or not according to a timing signal applied from timing generator 855 and a voltage value from program power supply 860.
The determination result is supplied to analysis memory 862 through functional test pattern generator 857. Analysis memory 862 stores the test result of devices under test DUT1 to DUTn supplied from functional test pattern generator 857. According to information on a defective cell address, a defect analysis circuit 863 carries out the redundancy analysis of devices under test DUT1 to DUTn, that is, analysis for finding an optimum address to be replaced.
As memories contained in a device under test have larger capacity, it becomes costly to provide a memory tester or the like with an analysis memory having the same capacity as the contained memories.
Considering a case where a plurality of devices under test are tested at the same time, the capacity of an analysis memory becomes extremely large and the test system is very expensive.
If the analysis memory is provided inside a semiconductor device, a test memory having the same space as the contained memory space is required. Since this doubles the chip area, it is meaningless to provide the analysis memory itself.
In order to efficiently repair a defective memory cell using a spare column and a spare row in the conventional art, the test system becomes very expensive as the memory capacity increases.